1. Field of the Invention
The present invention generally relates to reference voltage buffers, and more particularly to low-power, fast-reacting reference voltage buffers.
2. Description of Related Art
Reference voltage buffers are needed in numerous applications, e.g. pipeline ADC (analog-to-digital converter). The principles (e.g., structure and operation) of pipeline ADCs are well known in prior art and thus need not be described herein. For example, an illustrative pipelined ADC is described in U.S. Pat. No. 7,280,064. As described in U.S. Pat. No. 7,280,064, a pipeline ADC comprises a plurality of pipeline stages. A typical 1-bit pipeline stage 100 is depicted in FIG. 1. Pipeline stage 100 receives an input signal VI and generates an output signal VO and a 1-bit decision D. Pipeline stage 100 operates in accordance with a two-phase non-overlapping clock comprising a sampling phase Φ1 and a transfer phase Φ2. During the sampling phase (i.e., Φ1 is logically 1 and Φ2 is logically 0), the input signal is sampled into a first capacitor C1 and a second capacitor C2 via a first switch 125 and a second switch 121, respectively, where a termination to ground is provided for C1 and C2 by coupling the circuit node 150 to ground via a third switch 131. In the meantime, a polarity of the input signal VI is detected using a comparator 103, resulting in an intermediate signal S, and the 1-bit decision D is made by latching the intermediate signal S using a latch 105.
The pipeline stage 100 further comprises an operational amplifier 101, with a positive input terminal coupled to ground, a negative input terminal coupled to circuit node 150, and an output node 160 coupled to a third capacitor C3 to generate the output signal VO. During the transfer phase (i.e., Φ2 is logically 1 and Φ1 is logically 0), the second capacitor C2 effectively forms a negative feedback capacitor coupling between the negative input terminal and the output node 160 of the operational amplifier 101 via a fourth switch 123. In the meantime, a first logical signal EN_P is generated by performing an AND operation on the 1-bit decision D and the transfer phase clock Φ2 using a first AND gate 107, and a second logical signal EN_N is generated by performing an AND operation on DB (which is a logical inversion of the 1-bit decision D generated by an inverter 111) and the transfer phase clock Φ2. A first reference voltage VRP is coupled to the first capacitor C1 via a fifth switch 127 if the first logical signal EN_P is logically 1. A second reference voltage VRN is coupled to the first capacitor C1 via a sixth switch 129 if the second logical signal EN_N is logically 1. That is, during the transfer phase, the first capacitor C1 is coupled to VRP if the 1-bit decision D is 1, and coupled to VRN otherwise.
FIG. 2 depicts a typical circuit 200 for generating the two reference voltages VRP and VRN. Circuit 200 comprises: a current source IB, two resistors R1 and R2, two unity gain buffers 210 and 220, and two capacitors CP and CN. Throughout this disclosure VDD denotes a substantially fixed output voltage from a power supply. The current source IB along with the two resistors R1 and R2 determine two substantially fixed voltages VRP0 and VRN0. The two unity gain buffers 210 and 220 are embodied by two operational trans-conductance amplifiers (OTA) 211 and 221, respectively, configured in a non-inverting feedback topology. The two unity gain buffers are terminated with the two capacitors CP and CN, respectively, resulting in the two reference voltages VRP and VRN, respectively. In order for the reference voltages VRP and VRN to better hold their respective values upon a change of state of the switch capacitor 100 of FIG. 1, the two capacitors CP and CN must be much larger than the first capacitor C1 of FIG. 1.
Referring collectively to both FIG. 1 and FIG. 2, when the first logical signal EN_P is asserted, a charge is drawn from CP to C1, and the charge must be supplied by OTA 211 in order to maintain a constant level of the first reference voltage VRP. When the second logical signal EN_N is asserted, on the other hand, a charge is drawn from C1 to CN, and the charge must be absorbed by OTA 221 in order to maintain a constant level of the second reference voltage VRN. In order to quickly supply (absorb) the charge to make VRP (VRN) substantially constant, OTA 211 (221) must be a high-speed circuit. As is known, higher speed circuits typically consume more power.
Accordingly, what is desired is fast reacting buffer circuit to make a reference voltage substantially constant without consuming an excessive amount of power.